1. Field of the Invention
The present invention generally relates to systems for modeling the behavior of integrated circuits such as verifiers, simulators and design tools, and more particularly to a computer program that includes modeling of digital integrated circuit power supply pin current waveforms.
2. Description of Related Art
Design tools and verification tools are necessary for modeling large-scale digital integrated circuits such as Very Large Scale Integration (VLSI) circuits. Millions of transistors and logic gates are often combined on a single die and the performance of the die is modeled using software that models the performance of the overall die based on known (modeled) performance of individual gates, inverter/buffer models of gates, or models of larger functional blocks.
Power supply current for individual gates or blocks combines to generate the power requirements for the overall die, and will typically combine in sub-groups to several power and ground pins that are connected external to the integrated circuit package. The power supply pin connections are typically inductive, while the external power supplies to which the power pins connect are typically capacitive loads. The inductive pin characteristic leads to voltage noise as the changing power supply currents generate voltage drops across the pin inductances. Therefore, knowledge of power supply currents at power nodes of logic gates or larger functional blocks is valuable for knowing overall current consumption and time-dependent behavior and for induced/radiated noise modeling.
Present techniques for power supply node current modeling typically calculate power node current based upon a linear (ramp) model of input and output voltages. Since the predominant (typically  greater than 90%) component of power node current derives from output capacitance charging and discharging, the typical power node current model calculates the power node current as the output load capacitance times the slope of the output voltage waveform, which is further typically simplified as a risetime/load capacitance product. The linear output voltage ramp thus yields a step (pulse) current component in the model, although providing a useful approximation, is inaccurate in modeling power supply behavior and is generally unsuitable for noise analysis. Further, as power supply voltages are decreased (which is the trend for high-density integrated circuits to reduce power dissipation and noise), the linear input voltage risetime model is increasingly inaccurate.
While more accurate models may be produced using more detailed analog circuit analysis or waveshape fitting, the memory requirements and processing time are prohibitive for modeling large-scale circuits. Further, the analog and waveshape models are not directly compatible with existing power pin current models and logic gate models.
Therefore, it is desirable to implement an improved power node current waveform modeling algorithm. It would further be desirable to provide an algorithm that is compatible with existing power supply pin current and logic gate models.
The objective of providing an improved power node current waveform modeling algorithm is achieved in a method for modeling characteristics of a logical circuit block. The method generates an output voltage waveform of the logical circuit block by using a linear model that calculates points of the waveform from known points received as inputs. The inputs to the method are time values at which the output voltage reaches predetermined fractions of an input voltage signal. The time values are multiplied by coefficients from a set of coefficients for each output waveform point that are determined from a statistical model of logical circuit block behavior, yielding an output voltage waveform. The calculated output voltage waveform can then be differentiated and multiplied by a predetermined load capacitance to yield an output current waveform. The method retains compatibility with present timing simulators, as the delay time (taken as the 50% voltage point) and the rise time (which yields a difference of the 70% and 30% voltage points or other pair of voltage points) can be used to provide the input time values.
The invention may further be embodied in a workstation computer executing program instructions for carrying out the steps of the method, and in a computer program product having a storage media for those program instructions.
The foregoing and other objectives, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiment of the invention, as illustrated in the accompanying drawings.